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Advanced integrated circuits are approaching a key inflection point. However, the chip industry has never been eager to switch to a new transistor architecture for high volume chip production, as this entails new complexities and new investments. But recent public announcements from Samsung, Intel, TSMC and IBM show that we are on the verge of such a transition. From 2022 or 2023, these companies accepted that there had to be a gradual transition from state-of-the-art FinFET transistor architectures to nanosheet-like architectures to produce logic chips of the 3nm or 2nm technology generations.

What are the main drivers of this historic transition? We will answer them and present different generations of the nanosheet family of architectures, including nanosheets, forksheets and CFETs. For each of these members of the nanosheet family, we’ll go over the incremental benefits for further CMOS scaling and talk about critical steps in the process.

Why switch from FinFET to the nanosheet?
Along the path of logical CMOS scaling, the semiconductor community has made considerable efforts to gradually reduce the dimensions of standard logic cells.

One way to do this is to reduce the height of the cell – which is defined as the number of metal lines (or tracks) per cell multiplied by the metal pitch – by reducing the track. For FinFET, new generations with ever smaller cell heights were achieved by gradually reducing the number of fins in a standard cell from 3 to 2. This enabled standard 7.5T and 6T cells respectively. Ultimately, this trend will continue down to 1 fin, allowing standard 5T cells. With 6T, for example, we mean 6 metal lines fit the cell height range. This change, however, comes at the expense of drive current and variability. To compensate for the degradation in drive current and variability, the fins were getting higher in the cell height scaling.

However, it is extremely difficult to further improve the drive current of the unique finned device architectures based on FinFET 5T. And this is where nanosheet architectures come into the restricted scene. By vertically stacking nanosheet-shaped conduction channels in standard cells where only one fin is allowed, a larger effective channel width can be achieved. In this way, nanosheets can provide greater drive current per cavity than fins – a key benefit for further CMOS scaling. The nanosheet architecture also allows for variable device width, allowing flexibility in design: designers can now trade in improved drive current for reduced area and capacity (smaller channel width tends to reduce the parasitic capacity between the sheets). Another notable advantage of a nanosheet over a FinFET architecture is its complete gate structure: as the conduction channel is now completely surrounded by the high k / metal gate, better gate control over the channel is achieved. for shorter channel lengths.

Critical building blocks
Like the transition from planar MOSFETs to FinFETs, the transition from FinFETs to full-gate nanosheet transistors has come with new process integration challenges. Fortunately, the nanosheet can be seen as a natural evolution of FinFET and, therefore, many process modules developed and optimized for FinFET could be reused. This has certainly facilitated its adoption by the industry. Nevertheless, we identify four key stages of the process in which the two architectures differ, and which required specific innovations.

The first is that this architecture uses epitaxial multilayers of Si and SiGe to define the channel of the device. The use of cultured materials for the channel and the lattice offset between the two materials represent a departure from traditional CMOS device fabrication. In this multilayer stack, SiGe serves as a sacrificial layer which is removed later, during the release of the channel in the steps of replacing the metal gate. The entire multilayer stack is shaped as a high aspect ratio fin, which is a challenge to maintain good nanosheet shape. At the MEI 2017 conference, IMEC proposed a key optimization: the implementation of a shallow trench insulation coating (STI) and the use of a low thermal budget in the steps of the STI process to remove deformation fins induced by oxidation. This resulted in better control of the shape of the nanosheets, which was found to improve the performance of the device – DC (i.e. larger drive current) as well as AC (i.e. that is, a speed gain at constant power). The improved AC performance resulted in a lower gate delay of a ring oscillator circuit – which was the first report of an actual circuit made with the new nanosheet process flow.

Second, unlike FinFET, the nanosheet architecture requires an internal spacer – an additional dielectric that isolates the gate from the source / drain for reduced capacitance. During the step of the inner spacer forming process, the outer parts of the SiGe layers in the multilayer structure are hollowed out using a side etching process. This creates small cavities which are then filled with dielectric materials. The integration of the internal spacer is the most complex process module of the nanosheet process flow. It requires high engraving selectivity and precise lateral engraving control. The challenge of integrating the internal spacer has been addressed by several research teams around the world, including IMEC.

Third, there is the release of the nanosheet channel, the step where the nanosheets are separated from each other. This release is achieved by selectively etching the SiGe part of the multilayer. This step of the process requires highly selective etching, ideally leaving few Ge-restricted residues between the nanosheets and reducing the roughness of the Si. In addition, friction control is required to prevent these tiny nanosheets from attaching to each other. . IMEC’s ​​fundamental study of the various etching process options – wet and dry – went a long way in solving these problems.

And finally comes the step of integrating the replacement metal grid (RMG), including the deposition and structuring of the output function metal around and between the layers of nanosheets. In 2018, IMEC highlighted the importance of introducing a scalable working function metal, allowing reduced vertical space of the nanosheet stack. For example, the team showed that reducing the spacer between two vertical 13nm nanosheets to 7nm improved AC performance by 10%, highlighting the importance of scaling the RMG.

And then comes the fork leaf
The most elegant way to further increase DC performance is to increase the effective channel width. But in conventional nanosheet architectures, this becomes very difficult. The main obstacle is the large margin of space required between n-type and p-type devices, which makes it difficult to achieve a large effective nanosheet width in cell heights to scale. This space is consumed by a side overetch that occurs during the metal shaping step of the work function. The architecture of the forksheet device can meet this challenge. The forksheet was first offered publicly by imec for SRAM scaling in 2017 (MEI 2017), and later (MEI 2019) as a catalyst for standard logical cell scaling [5, 6]. In this architecture, a smaller np separation is allowed by introducing a dielectric wall between the n- and pMOS devices before structuring of the gate. This dielectric wall now serves as an etch stop layer to shape the work feature metal, allowing for a much tighter n-to-p spacing. Therefore, the effective width of the channels – and therefore the drive current (DC performance) – can be further improved. Instead of maximizing the effective channel width, the smaller n-to-p space can also be exploited to further extend the track height of the standard airframe from 5T to 4T. This evolution must be complemented by innovations in the back-end and middle-of-line, and by the introduction of scaling boosters (such as buried power rails or self-closing door contacts. aligned).

The simulations also predict an AC performance gain of 10% for fork sheets compared to nanosheets. The imec team could explain this speed improvement by a reduced Miller (parasitic) capacitance resulting from a smaller gate-drain overlap. The small Miller cap potentially allows for more energy efficient devices.

From a processing point of view, the forksheet architecture evolves naturally from the “base” architecture of nanosheets. The key differentiators are the dielectric wall formation and steps of modified interior spacing, source / drain epitaxy, and replacement metal gate. At VLSI 2021, IMEC presented for the first time the electrical data of the fork leaf field effect devices which were successfully integrated using the 300mm fork leaf process flow. Dual working metal grids could be integrated at 17nm spacing between n- and pFETs, highlighting the key advantage of the forksheet architecture.

There was, however, still a concern about electrostatics. Nanosheet architectures are touted for their all-around gate structure, which greatly improves electrostatic control over the channel. With its tri-gated fork-shaped architecture, the forksheet seems to be stepping back. However, in the experiments mentioned above, IMEC found short channel control (SSSAT = 66-68mV) at a gate length of 22nm which was comparable to that of vertically stacked nanosheet devices which were co-integrated on the same plate.